Successive approximation is a conversion method which is used for medium-speed analog/digital converters (A/D) [U. Tietze—Ch. Schenk, Halbleiterschaltungs-technik [Semiconductor Circuit Engineering], 10th edition, p. 780 ff].
FIG. 5 shows the basic construction of a known analog/digital converter 500 with a weighing method and with successive approximation. The analog/digital converter 500 has a sample & hold element 502 for sampling and storing an analog input signal UE, and a comparator 504 for comparing the stored input signal UE with the analog output signal U(Z) from a digital/analog converter 506. The sample & hold element 502 is needed to store an input signal UE temporarily in order that changes in the input signal UE during the conversion period do not cause any errors.
At the beginning of a conversion, the number Z at the input of a digital/analog converter (506) is set to zero. The most significant bit (MSB) is then set to one and a check is made to see whether the analog input signal UE of the analog/digital converter 500 is greater than U(Z) . If this is so, the bit remains set. Otherwise, it is reset again. The most significant bit is therefore “weighed”. This weighing operation is then repeated for each further bit until, at the conclusion, the least significant bit (LSB) has also been fixed. In this way, in a register 508, which is also referred to as a register for a successive approximation (SAR; SAR=Successive Approximation Register), a number is produced which, after conversion by the digital/analog converter 506, results in a voltage U(Z) which agrees with the analog input signal UE within a resolution for the least significant bit ULSB. The register 508 typically comprises flip-flops, which are connected up to form a shift register.
The maximum conversion speed of the analog/digital converter 500 of FIG. 5 is determined by the fact that the n-bit digital/analog converter 506 has to make n decisions, each of these decisions having to be as accurate as the final conversion result itself. The digital/analog converter 506 has to supply n comparison values U(Z) for each conversion of an input signal UE, time of course being used until these n comparison values U(Z) are generated by the digital/analog converter 506 with the desired accuracy. The digital/analog converter 506 swings approximately exponentially to the desired value u=U0(1−e−t/τ). In addition, the comparator 504 needs time to compare the comparison values with the analog input signal UE to be converted. This time depends on the step height of the analog input signal UE. The time needed by the digital/analog converter 506 to swing to a ½ LSB is given by
  t  =      τ    ×          ln      ⁡              (                              1            2                    ×                      1                          2              n                                      )            
In order to increase the conversion speed of an analog/digital converter, a larger error can be permitted during each conversion step, which leads to the converters already known which have redundant code.
An analog/digital converter with redundant code is produced from a binary analog/digital converter when the elements, such as resistors, with which the reference value, for example a reference voltage, is divided in order to supply comparison values, are not weighted in a binary manner but are weighted with a smaller numeric base than 2. There are therefore a plurality of codes relating to one and the same analog value, and as a result small wrong decisions have no influence on the conversion result. In the case of a conventional binary converter without redundancy, for example the MSB, if it is wrongly set by an error, can no longer be corrected in the subsequent conversion steps. In the case of an analog/digital converter with redundant code, if the error is not too great, there is a second code which corresponds to the same analog input signal.
In the case of an analog/digital converter with redundant code, the digital/analog converter is constructed, for example, not by using a reference element, a reference element of twice the size, a reference element of four times the size; instead multiplication is carried out with a value smaller than 2. In this case, the reference elements can have, for example, the weighting 1; 1.8; 1.8×1.8; 1.8×1.8×1.8, etc. Here, reference elements can be, for example, capacitors, current sources, resistors, etc.
The analog/digital conversion is then carried out in such a way that, firstly, the analog value to be converted or the analog input signal is stored. The analog value is then compared with somewhat more than half the reference value, by the largest reference element and, in addition, one or more smaller reference elements being set in the digital/analog converter. If, for example, the numeric base 1.8556 is used, the attempt can be carried out by using 1000100 . . . If the analog value to be measured is greater than the comparison value, the leading 1 remains set, and the next comparison is carried out by using 1100010 . . . If the analog value is smaller, then the MSB is set to zero, and the next comparison is carried out by using 0100010 . . . In the case of this algorithm, a redundant code is produced in which there are a plurality of codes relating to one and the same analog value. An error which occurs in the MSB can as a result be compensated for in the subsequent conversion steps.
FIG. 6 shows a known analog/digital converter with redundant code. The analog/digital converter 600 has an arrangement 602 of reference capacitors 604 with fixed weighting 1 p; 1.8556 p; 3.4432 p; 6.3892 p and 11.8559 p, which forms a digital/analog converter. A reference voltage UREF can be applied to this arrangement 602 of reference capacitors 604 as desired via switches 606 either to sample an analog input voltage UE or to produce a comparison voltage to be compared with the analog input voltage. The analog/digital converter 600 also has a comparator 608, at which the input voltage UE and the comparison voltage produced from the reference voltage UREF can be compared at inputs 610 and 612. The comparator 608 can be bypassed by switches 614 and 616, in order to sample and to store the input voltage UE at the start of a conversion. During a comparison by the comparator 608, the result of the comparison is passed on to a register 618 with successive approximation (SAR) which, on the basis of the result of the instantaneous comparison, drives and selects the reference capacitors 604 of the arrangement 602 for the next comparison in such a way that a gradual approximation (successive approximation) to the actual input voltage UE is achieved. The comparison and gradual approximation is carried out down to the least significant bit (LSB). Once the result of the conversion has been achieved, then the register 618 passes on the value determined, which is encoded with the redundant code, to an adder 620. The adder 620 calls up the reference capacitance values of the arrangement 602 from a memory 622 and, by means of addition with an adder 620, corrects the value determined in the redundant code in order to produce a binary value. An accumulator register AKK REG 624 stores the binary encoded value as the result of the analog/digital conversion and outputs it.
One disadvantage of the analog/digital converter 600 of FIG. 6, which has reference elements that are not binary-weighted but weighted with a smaller numeric base than 2, is that such reference elements, which have a base value of 1.8556, for example, as shown in FIG. 6, cannot readily be produced by doubling etc. of the basic reference element. This is because, in the layout of a circuit for an analog/digital converter, odd reference values are more difficult to implement than simple doublings, as in the case of binary weighting. The result is therefore in principle greater errors than in the case of a binary analog/digital converter.
A further disadvantage of the analog/digital converter 600 of FIG. 6 is that the redundant code has to be converted into a binary code in the adder 620 for further use. Rounding errors occur in the process.
A further disadvantage of the analog/digital converter 600 of FIG. 6 is that, in the case of a redundant code, smaller reference capacitors often have to be disconnected and larger reference capacitors have to be connected in order to produce a comparison value, that is to say many switching operations occur, which make it necessary to recharge capacitors and therefore lead to an increased power consumption of the analog/digital converter.